Semiconductor component manufacturers are constantly striving to increase the speeds of their components. Because a semiconductor component, such as a microprocessor, contains up to a billion transistors or devices, the focus for increasing speed has been to decrease gate delays of the semiconductor devices that make up the semiconductor component. As a result, the gate delays have been decreased to the point that speed is now primarily limited by the propagation delay of the metallization system used to interconnect the semiconductor devices with each other and with elements external to the semiconductor component. Metallization systems are typically comprised of a plurality of interconnect layers vertically separated from each other by a dielectric material and electrically coupled to each other by metal-filled vias or conductive plugs. Each layer contains metal lines, metal-filled vias, or combinations thereof separated by an insulating material. A figure of merit describing the delay of the metallization system is its Resistance-Capacitance (RC) delay. The RC delay can be derived from the resistance of the metal layer and the associated capacitance within and between different layers of metal in the metallization system. More particularly, the RC delay is given by:RC=(ρ*εl2/(tm*tox))where:                ρ is the resistivity of the metallic interconnect layer;        ε is the dielectric constant or permittivity of the dielectric material;        l is the length of the metallic interconnect;        tm is the thickness of the metal; and        tox is the thickness of the dielectric material.        
Thus, the RC delay of the metallization system may be reduced by decreasing the resistivity of the metal comprising the metallization system. Because copper has a lower resistivity than other metals that are compatible with semiconductor processes, semiconductor component manufacturers have begun using metallization systems comprising copper. A drawback with copper is that it is difficult to etch. To mitigate this difficulty, single and dual damascene processes have been developed in which trenches and vias are etched into a dielectric material and then lined with a conformal layer of a barrier material having a uniform thickness. The barrier material prevents diffusion of copper through the sidewalls of the trenches and vias. A single-metal seed layer is formed on the barrier layer and acts as a cathode for electroplating a thick copper layer on the barrier layer. It is desirable for the single-metal seed layer to be a conformal layer having a uniform thickness. However, single-metal seed layers produced using Plasma Vapor Deposition (PVD) have a non-uniform thickness. Thus, the seed layer may be too thin, or absent from portions of the barrier layer, resulting in the formation of voids during the copper electroplating process. Voids increase the resistance of the metallization system. Alternatively, the seed layer may be too thick resulting in pinching or closure of vias lined by the seed layer. Single-metal seed layers produced using Chemical Vapor Deposition (CVD) are formed using halogens which inhibit the seed layer from adhering to the underlying barrier layer. Seed layers formed using Atomic Layer Deposition (ALD) are reduced using a high temperature thermal treatment, which causes the copper atoms in the seed layer to agglomerate. The agglomerated seed layer produces a discontinuous current path during the electroplating step resulting in inadequate copper formation over the seed layer. In addition, agglomeration may expose portions of the barrier layer to oxygen present in the surrounding ambient which oxidizes the exposed portions of the barrier layer. Voids may be formed in the portions of the copper above the oxidized barrier layer.
Accordingly, what is needed is a semiconductor component having a metallization system with a conformal seed layer of uniform thickness and without gaps or discontinuities and a method for manufacturing the semiconductor component.